1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a MOS device having a salicide gate electrode and source/drain regions.
2. Description of the Related Art
As MOS devices have been scaled down to improve performance, the gate length of a gate electrode, i.e., the channel width has been shortened, and the junction depth of source/drain impurity diffusion regions has been shallowed. Therefore, the sheet resistances of the gate electrode and the source/drain impurity diffusion regions have been increased. As a result, the parasitic resistances of the gate electrode and the source/drain impurity diffusion regions have been increased in proportion to the channel resistance, thus decreasing drain current.
In order to suppress the decrease of the drain current, a first prior art method for manufacturing a salicide MOS device has been suggested (see: JP-A-2-288236). That is, a metal silicide layer is formed on the gate electrode and the source/drain impurity diffusion regions, thus reducing the parasitic resistances of the gate electrode and the source/drain impurity regions. This will be explained later in detail.
In the first prior art manufacturing method, however, since the metal silicide layer on the gate electrode is as high as a sidewall insulating layer formed on a sidewall of the gate electrode, if the metal silicide layer is extremely grown, a short circuit may occur between the gate electrode and the source/drain regions.
In a second prior art method for manufacturing a salicide MOS device (see: J. R. Pfiester et al., "A Self-Aligned Elevated Source/Drain MOSFET", IEEE Electron Device Letters, Vol. 11, No. 1, pp. 365-367, September 1990, and M. Sekine et al, "Self-Aligned Tungsten Strapped Source/Drain and Gate Technology Realizing the Lowest Sheet Resistance for Sub-quarter Micron CMOS", IEEE IEDM digest. abs. 19.3.1, pp. 493-496, 1994), a gate insulating layer, a polycrystalline silicon gate electrode layer and a silicon nitride layer (or a phosphosilicated glass (PSG) layer) are formed on a monocrystalline silicon substrate. A sidewall insulating layer is formed on a sidewall of the silicon nitride layer (or the PSG layer) and gate electrode layer. Then, impurties are introduced into the substrate with a mask of the sidewall insulating layer and the silicon nitride layer (or the PSG layer), thus forming source/drain impurity diffusion regions in the substrate. Then, the silicon nitride layer (or the PSG layer) is etched out by hot phosphoric acid (or diluted HF solution). Finally, a metal layer is formed on the entire surface, and a heating operation is carried out, so that metal silicide layers are formed on the gate electrodes and the impurity diffusion regions. Thus, the height of the metal silicide layer on the gate electrode layer is smaller than that of the sidewall insulating layer, so that the gate electrode layer is electrically isolated from the source/drain regions. Thus, no short circuit may be generated between the gate electrode layer and the source/drain regions. This will be explained later in detail.
In the second prior art manufacturing method, however, since the selectivity of etching for the silicon nitride layer (or the PSG layer) against the other silicon oxide layers is inferior, a short circuit may be generated between the gate electrode layer and the source/drain regions. On the contrary, if the etching of the silicon nitride layer (or the PSG layer) is insufficient, the growth of metal silicide is impeded.